The Evolution of Heterogeneous Integration and Chiplet Technology in High-Performance Computing

Abstract

In the post-Moore’s Law era, as the size of transistors gets smaller, the traditional chips are reaching physical limits. Chiplet technology can get better performance and yield without shrinking transistors. Today, Artificial Intelligence (AI) and High-Performance Computing (HPC) need faster chips. So the development of Heterogeneous Integration and chiplet technology are increasingly significant. This paper discusses the evolution of chip packaging technologies and compares the advantages and disadvantages of 2D, 2.5D and 3D packaging. It also discusses the technologies and design of chiplets such as modular functional partitioning design and Die-to-Die (D2D) chiplet interface technology. At present, chiplet is still under development, so this paper lists the challenges like thermal and signal integrity problems. In the future, the chiplet will have wider open standards, higher performance and more application fields. In conclusion, the chiplet will be the key way to improve HPC in the post-Moore’s Law period.