FPGA Dynamic Partial Reconfiguration for Energy-Efficient Data Centers

Abstract

As the number of parameters in deep learning models grows exponentially, the energy consumption of AI computing power in data centers are becoming increasingly serious. Under highly fluctuating cloud request loads in data centers, static hardware acceleration architectures often face energy efficiency issues such as idle computing power and energy degradation under low load. This paper provides a comprehensive overview of the application of FPGA dynamic partial reconfigurable (DPR) technology proposed in recent years in optimizing AI energy efficiency in data centers, covering underlying reconfiguration technologies, runtime optimization strategies, multi-dimensional evaluation frameworks (energy, power and carbon awareness), as well as current challenges and future research directions. Meanwhile, we discuss how carbon-aware metrics can be incorporated into future evaluation frameworks for reconfigurable FPGA accelerators, thereby providing a reference for energy efficiency optimization research of data centers.